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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
235
(4) Cycle measurement
By setting the TMCn0 and TMCn1 registers as shown in Figure 7-15, the 16-bit timer/event counter can
measure the cycle of signals input to the INTPn0 or INTPn1 pin.
The valid edge of the INTPn0 pin is selected according to the IESn01 and IESn00 bits of the SESn register,
and the valid edge of the INTPn1 pin is selected according to the IESn11 and IESn10 bits of the SESn register.
Either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins.
If the CCn0 register is set as a capture register, the valid edge input of the INTPn0 pin is set as the trigger for
capturing the TMn register value in the CCn0 register. When this value is captured, an INTCCn0 interrupt is
generated.
Similarly, if the CCn1 register is set as a capture register, the valid edge input of the INTPn1 pin is set as the
trigger for capturing the TMn register value in the CCn1 register. When this value is captured, an INTCCn1
interrupt is generated.
The cycle of signals input to the INTPn0 pin is calculated by obtaining the difference between the TMn
register’s count value (Dx) that was captured in the CCn0 register according to the x-th valid edge input of the
INTPn0 pin and the TMn register’s count value (D(x+1)) that was captured in the CCn0 register according to
the (x+1)-th valid edge input of the INTPn0 pin and multiplying the value of this difference by the cycle of the
internal count clock.
The cycle of signals input to the INTPn1 pin is calculated by obtaining the difference between the TMn
register’s count value (Dx) that was captured in the CCn1 register according to the x-th valid edge input of the
INTPn1 pin and the TMn register’s count value (D(x+1)) that was captured in the CCn1 register according to
the (x+1)-th valid edge input of the INTPn1 pin and multiplying the value of this difference by the cycle of the
internal count clock.
Remark
n = 0, 1
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